Technical Product Information for the DAP 4200a™

The DAP 4200a/526 model

• has an Intel i486 DX4 processor onboard
• provides 14-bit A/D converter resolution
• works with the 5V PCI bus for Pentium/Pentium II platforms
• comes with 16M of DRAM onboard memory
• transfers data to PC at high rates -- up to 3.2M samples per second
• offers low latency -- 0.2 ms task time quantum -- for fast response
• offers sampling period resolution to 100 ns
• samples or updates the digital section at up to 1.66 million values per second
• samples analog inputs at up to 769K samples per second at 12-bit accuracy
• updates analog outputs at up to 833K samples per second each
• provides onboard emulation of DSP routines
• provides the same input and output voltage ranges as the DAP 3200a
• allows fast real-time processing
• is compatible with other a Series boards
• has expandable analog and digital inputs/outputs
• complies with the European EMC Directive and is CE marked

There is only one DAP 4200a model: the DAP 4200a/526. This technical note describes features and architecture of the DAP 4200a.

The DAP 4200a provides 14-bit A/D resolution for its 16 onboard analog inputs, and 12-bit D/A resolution for its 2 onboard analog outputs. The onboard analog input channels sample at an overall 769k samples per second at 12-bit accuracy, and sample at 588k samples per second at 14-bit accuracy. The 16 onboard digital input channels sample at an overall rate of 1.66M words per second.

The DAP 4200a has a PCI host interface, and is capable of high speed data transfers to the host PC. The DAP 4200a requires a 5V 32-bit PCI slot. Using bus mastering DMA transfers, the DAP 4200a can trans-fer data to the host PC at 3.2M samples per second. This transfer rate is more than three times faster than that of the DAP 3200a.

The onboard multitasking operating system, DAPL, runs on the DAP 4200a, and ensures that hardware-level differences are transparent. DAPL 2000 is a complete software environment for real-time data acquisi-tion. Tasks that perform averaging, triggering, PID control, fast Fourier transforms, filtering, arithmetic operations and many other functions are pre-coded in DAPL. These tasks are chained together to form a complete data acquisition application. To aid application development, DAPL has many system diagnostics in addition to automatic memory and system checks that are done at initialization.

Much of the DAP 4200a design is similar to that of the DAP 3200a/415. The DAP 4200a uses the same type of analog and digital connectors as the DAP 3200a, so the DAP 4200a is compatible with all the same cabling and external boards for termination and expansion. Accessories used with any a-Series Data Acquisition Processor can be used with the DAP 4200a.

The DAP 4200a provides the same level of processing performance as the DAP 3200a/415, but offers more memory. The DAP 4200a has an onboard Intel 486 DX4 processor running at 96MHz, and has 16Mbyte of memory. The PCI bus allows the DAP 4200a to transfer data to the PC at high rates -- up to 3.2M samples per second.

Figure 1: DAP 4200a Data Acquisition Hardware

Figure 1 displays the hardware architecture of the DAP 4200a. The figure shows that the PCI host interface is connected directly to the processor bus. This intimate connection allows fast and efficient data transfers to the host PC. The figure also shows the two FIFOs on the DAP 4200 that handle data acquisition. The data FIFOs are unidirectional, buffering data for input and output.

Data are acquired or updated via dedicated hardware clocking circuitry at a rate of up to 1.66 million samples per second. Acquisition is clocked at a sampling rate or output rate controlled in software, and the rate is accurately maintained by onboard crystal-controlled timers. The sample period is specified with a resolution of 100 nanoseconds and the sample rate is accurate to 50 parts per million.

In addition to onboard timing, the DAP 4200 also has provisions for external triggering and clocking for the input and output sections. The DAP 4200a has an improved input sampling pipeline. Data are sampled and read by the processor in the same input clock cycle.

The 16-bit digital input port and the analog-to-digital converter are attached to the Input Data FIFO, one of the unidirectional data FIFOs. The maximum aggregate sample rate is 1.66M samples per second. Digital input alone can run at up to 1.66M samples per second. The maximum analog input sample rate is 769K samples per second.

The digital output port and the two analog outputs are attached to the Output Data FIFO. The maximum aggregate update rate is 1.66M updates per second. Digital output alone, like digital input, can run at up to 1.66M updates per second. Each of the analog outputs can be updated at 833K updates per second.

The Bypass section shown in Figure 1 allows the processor to asynchronously update either the digital or analog outputs. This means that periodic timing is not guaranteed, rather the processor will attempt to update the outputs whenever a time slice for this task becomes available. This is useful in control application where a digital output, for example, needs to open or close a valve at irregular intervals.

In addition to the processor and data transfer hardware, some important hardware specifications of the DAP 4200a are provided in Table 1 below.

¹ The sampling rates are for 12-bit accuracy. The gain 1 sampling rate for 14-bit accuracy is 588k samples/sec.

² The DAP 4200a can update each of its two standard analog outputs independently at 833k updates per second. When analog output expansion is used, the update rate for expanded channels is determined by the maximum update rate of the digital port.

³ This figure is the maximum throughput of simultaneous digital input and output. Either digital input or digital output operating alone can maintain a throughput of 1.6M words/sec.

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